Cadence Info Session

Cadence Info Session
Speaker: Janet Olson, VP R&D – Front End Design, Cadence Design Systems
Date : September 30, 2019
Time: 5:00pm - 6:00pm
Location: Gates Building, Room 104

Bring your resume to enter into the raffle drawing!

RSVP via Handshake:

Janet will be speaking about the advances and challenges in the EDA industry


Janet Olson is the Vice President of Front End Design and Implementation at Cadence Design Systems. Recipient of the 2017 Marie R. Pistilli Women in ENGINEERING Achievement Award and YWCA Silicon Valley Tribute to Women Award, Janet has been active in engaging and advancing women within the electronic design automation (EDA) industry. Janet holds a Bachelor’s degree in Electrical Engineering from Carnegie Mellon and a Master’s degree in Electrical Engineering from Stanford University. Prior to joining Cadence, Janet was the VP of Engineering at Synopsys.

Monday, September 30, 2019 - 5:00pm to 6:00pm
Gates Computer Science, 353 Serra Mall, Stanford, CA 94305, USA